Figure 4

Block diagram of the signal processing. The analogue output pulse of the PMT is first amplified and then converted by the CFD into a digital signal. The signal of channel B is delayed by 2 ns. Within the majority logic, signal A is stretched to 8 ns while signal B is stretched to 4 ns. If both signals occur at the same time, channel 3 of the majority logic (configured as logic AND) produces a digital output pulse. This pulse is finally regarded as annihilation event.